How to evaluate the clock cycle for MIPS single cycle CPU

Problem Detail: 

The Situation

I'm trying to read the book 'Digital Design Computer Architecture'.
In the part of Performance Analysis(7.3.4 in the book), Author refers to clock cycle for MIPS single cycle processor. But I think there's something wrong with author's evaluating clock cycle.

Author says,

T(Clock cycle) = T(pcq_pc) + T(mem) + Max[tRfread, t(sext)] + t(Mux)                    + T(ALU) + T(mem) + t(mux) + T(RFsetup) 

But I think clock cycle 'T' would be ( if T(RFread) > T(mux) + T(sext) )

T(Clock cycle) = T(pcq_pc) + T(mem) + T(RFread) + T(ALU) + T(mem) + T(mux) + T(Rfsetup) 

Since I think the MUX followed by ALU already selects known sign-extend immediate before register value(the pin RD1 in below diagram) is known.

and if T(RFread) is less than T(mux) plus T(sext).

T(Clock cycle) = T(pcq_pc) + T(mem) + T(sext) + T(Mux)                    + T(ALU) + T(mem) + T(mux) + T(RFsetup) 

Some referenced information by the book.

• T(pcq_pc) is propagation delay for PC.
• T(mem) is read-propagation delay for instruction memory and data memory.
• T(sext) is propagation delay for Sign Extend logic.
• T(RFread) is read-progagation delay for register file.
• T(mux) is propagation delay for MUX.
• T(ALU) is propagation delay for ALU.
• T(RFsetup) is setup time for Register file.(Register value is written on positive clock edge)

Here is Diagram for MIPS single cycle CPU.

Is my thought correct? If you think author is right, Could you tell my why?
Any help would be awesome!

Asked By : inherithandle

Answered By : Wandering Logic

Now that you have (dramatically) modified your question:

The author of the book is correct. RD1 can not be on the critical path because the time to read RD1 is the same as the time to read RD2, but then RD2 needs to go through the mux in front of the ALU. If the time to read RD2 > T(Sext) then RD2 is on the critical path, if T(Sext) > T(RFread) then Sext is on the critical path. That's what the Max() operator does. Either way T(mux) needs to be in the expression.

Your last expression with T(Sext) +T(mux) is the same as what the author's expression gives in the case that T(Sext) > T(RFread). But your middle expression is wrong: if T(RFread (the read of RD1)) > T(Sext) + T(mux) then T(RFread (the read of RD2)) + T(mux) > T(Sext) + T(mux) + T(mux) > T(Sext) + T(mux). So you need to have T(mux) in the expression no matter which T(RFread) or T(Sext) is larger.

The basic rule (which you are mostly correctly following) is: use Max() for things that proceed in parallel, + for things that follow in sequence. The mux comes after both the Sign extend and after the read of RD2.

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Question Source : http://cs.stackexchange.com/questions/11338