[Solved]: Understanding Multilevel Caches

Problem Detail: 

I'm reading multi-level cache and came across a question through which i got confused. I've read that

• Between processor and Cache Word/ Byte is transfered
• Between Cache and Main memory Block(Block of words) is transfered.
• If there is a miss in lower level cache and hit in higher level cache, first Block of words is transfered from higher level cache to lower level cache and then particular words is transferred to the ptocessor from lower level cache.

In case of multi-level caches cache at lower level generally has lower size as compared to cache at higher level. Hence Block size of lower level cache is generally smaller than block size of higher higher cache.

So, How actually Block of words is transferred between caches.

For instance suppose there two caches $L_1$ and $L_2$ with block size 4 words and 16 words respectively, connected with a databus having capacity to transfer 4 words at a time. Now Suppose there is a miss in $L_1$ cache and a hit in $L_2$ cache. Then Do we transfer 16 words or only 4 words from $L_2 \rightarrow L_1$

Asked By : Atinesh

Answered By : ultrajohn

It depends. What is the level of associativity of L1? If it's a direct mapped cache, then naturally, you will have to transfer 4 words of data from L2 to L1. If it's a 2-way set associative, then 8 words. This makes the interface between L1 and L2 as simple as possible given their configurations.

The idea is to make the hit time of L1 and miss rate of L2 as low as possible.

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Question Source : http://cs.stackexchange.com/questions/37375