Difference between memory access and write-back in RISC pipeline

Problem Detail: 

I'm a little confused about the difference of the memory access and the write-back stage in a RISC pipeline.

We learned in class these following assumptions:

arithmetic & logic: IF, OF, EX, WB load: IF, OF, EX, MA, WB store: IF, OF, EX, MA branch: IF, OF, EX  IF=Instruction Fetch, OF=Operand Fetch, EX=Execution, MA=Memory Access, WB=Write-Back 

Lets say we have the following code now:

I1: LD R1, 0(R2) ; load R1 from address 0 + R2
I2: ADD R1, R1, #1 ; R1 = R1 + 1
I3: ST 0(R2), R1 ; Store R1 at address 0 + R2

According to what I've learned I1 will pass all five stages, I2 won't have to access the memory, and I3 won't have a write-back.

But then I wonder, how and where does I3 store the value then? Just in the memory? And I2 fetches the value from memory, but needs to write-back to some place other than the memory? So does that mean that write-back is always to the HDD?

I think I'm missing some core concepts here, as to where the operand is fetched from and where it gets stored to.

Asked By : Stanley Fox

Answered By : Pseudonym

In a classic 5-stage RISC pipeline, WB writes a value into a register. If the instruction doesn't write a value into a register (e.g. store), then that stage isn't used.

I1 stores a result into a register (namely R1), so it uses WB.

I2 stores a result into a register (R1) so it uses WB.

I3 does not store a result into a register, so it doesn't use WB.

You basically got it with I3: the store instruction stores to memory, so the "write" is performed inside MA.

Incidentally, on "real" RISC machines, MA tends to be more complex (and multi-cycle) because of multi-level caches and virtual memory. A store instruction may cause a page fault, so in a sense it has a "result" that isn't just the memory access.

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Question Source : http://cs.stackexchange.com/questions/19668