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In instruction pipelining, can we forward an operand more than one clock cycle?

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Problem Detail: 

Most operand forwarding examples that use the standard 5-stage MIPS pipeline forward operands from EX or MEM by ONE clock cyle to a later instruction. Is it possible to do so for more than one (from the 5th to the 8th clock cycle, for example)?

Asked By : curious

Answered By : nic

Paul's Comment is correct: "Yes. This is one way of avoiding a structural hazard on the write ports of the register file with operations of several different latencies (i.e., having a single writeback stage for all operations). However, adding forwarding paths increases wiring and operand selection complexity."

In general, the amount of hazards and amount of opportunities for forwarding increase with pipeline depth. So a 10-stage pipeline will yield more hazards and more theoretical opportunities for forwarding than a 5-stage pipeline. However, the control logic to detect and schedule all the forwarding increases significantly (likely with a polynomial factor).

The distance of stages you can forward an operand is justified by the minimum of the two following things:

  • The number of forward stages until the operand enters the register file.
  • The number of reverse stages where the operand could logically be used.

In other words, it makes no sense to attempt to perform 5 cycles of forwarding on a 5-stage pipeline since all operands would have been in the register file anyway.

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